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Presentation

Tutorial
:
A Practical Approach to Application Performance tuning with the Roofline Model
Event Type
Tutorial
Passes
Tags
Computer Architecture
Energy consumption
Parallel Applications
Performance Analysis and Optimization
Performance Tools
TimeSunday, June 24th2pm - 6pm
LocationAnalog 2
DescriptionThe Roofline performance model offers an insightful and intuitive method for measuring key characteristics of HPC applications and determining the performance bounds of modern platforms and micro-architectures. Its capability to abstract the complexity of modern non-uniform memory hierarchies and identify the most profitable optimization techniques has made Roofline an increasingly popular analysis tool in the HPC community. Although different flavors of the roofline model have been developed to deal with various definitions of memory data traffic (by some of the contributors and presenters of this tutorial), there is still need for a more systematic methodology when applying them to analyze the efficiency of applications in multi/many-core systems. The tutorial aims to bridge this gap by exposing the fundamental aspects behind different Roofline modeling principles and providing practical use-case scenarios and pen-and-paper examples to show their usability for application optimization. This tutorial presents a unique combination of novel methodologies applied to optimize a representative set of open science use cases, while hands-on training with Intel Advisor is given by the lead methodology researchers and main designers of Intel’s Roofline automation tools. The tutorial presenters have a long experience working with the Roofline model and have presented several Roofline-based tutorials.
Content Level 30% Introductory: Roofline methodology 40% Intermediate: Roofline Automation, Hands-on Demo 30% Advanced: use cases and optimization of Complex Scientific Applications
Target Audience A very large segment of ISC’18 attendees, i.e., from research scientists and software developers to computer science experts and micro-architecture designers. In particular, HPC users and/or software developers with a good knowledge of parallel programming models who are interested in optimizing code performance on diverse architectures
PrerequisitesAttendees need laptops to participate in the hands-on. Hands-on material will be provided on USB sticks and online.