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Said Derradji is the coordinator of the Mont-Blanc 2020 project. As a hardware architect at Bull (Atos group), Said Derradji worked first on several custom ASIC designs interconnecting processors and focusing on cache coherency. He also worked on board design and participated to the TERA-100 system delivery in 2011 (ranking 9 in Top500.org). Since 2012, he has been working in the hardware architecture team at Bull, which specified the open exascale supercomputer, code-named SEQUANA. His areas of expertise are ASIC/FPGA design, HPC servers architecture and high performance interconnect technology such as BXI (Bull Exascale Interconnect). He is Bull’s representative at the PCI-SIG (PCI Special Interest Group) and in the IBTA (InfiniBand® Trade Association) consortiums. He was involved in the Mont-Blanc 2 project, as is now leading an architecture Work Package in the Mont-Blanc 3 project.