Dr. Williams received his Ph.D. in Computer Science from the University of California at Berkeley (UCB) in December of 2008 and his masters in December of 2003. During this period, his doctoral research focused on multicore architectures and automated performance tuning under the guidance of David Patterson. To that end, he worked in several Parallel Computing Laboratory (ParLab) research groups including: BeBOP, Architecture, and the Berkeley View. In January of 2005, Sam received an appointment as a GSRA in LBL's Future Technologies Group (FTG) under Kathy Yelick. The IRAM project was the focus of his masters research. He implemented the RTL for the integer and floating-point datapaths, verified the simulators and all RTL, floorplanned the entire VIRAM1 chip, and performed all necessary place-and-route (PnR) work. His coursework at UCB focused on high-performance, dependable computing with minors in embedded system design and astronomy.
Performance Analysis and Optimization