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DTSTAMP:20191206T142451Z
LOCATION:Analog 1\, 2
DTSTART;TZID=Europe/Stockholm:20180625T132100
DTEND;TZID=Europe/Stockholm:20180625T132500
UID:isc_hpc_ISC High Performance 2018_sess103_phd120@linklings.com
SUMMARY:(PhD06) A First Principles Approach to Performance and Power Model
 s for Contemporary Multi- and Many-Core Processors
DESCRIPTION:PhD Forum\n\n(PhD06) A First Principles Approach to Performanc
 e and Power Models for Contemporary Multi- and Many-Core Processors\n\nHof
 mann\n\nThe scientific objective of the research is to better understand p
 erformance,\npower, and energy properties of contemporary HPC processors t
 hrough analytical\nmodeling. The practical objective is to develop models,
  best practices, and\ntools related to performance, power, and energy mode
 ling and engineering.\n\nCurrent results include the extension and refinem
 ent of the original ECM\nmodel, as well as the development of quantitative
  power and energy models.\n\nThe ECM model was originally developed for Sa
 ndy Bridge processors.  This\nmodel was ported to and evaluated on the Int
 el Haswell, Broadwell, Skylake,\nAMD Zen, and IBM POWER8 processors. This 
 required modeling of the following\ncomponents/features: store-through and
  victim caches; IBM's Centaur memory\nbuffer chip; partial and full overla
 p of transfers in the cache/memory\nhierarchy; streaming stores; cluster-o
 n-die mode; separate clock domains (core\nvs. Uncore frequency); impact of
  variable Uncore frequency on L3 and memory\nbandwidths. Further the memor
 y bandwidth model was refined to take into\naccount reduced throughput wit
 h increasing bus utilization, fixing a problem\nwith multi-core performanc
 e estimates near the saturation point (where earlier\nrelative model error
 s of 20+% were reduced below 1%).  Apart from an accurate\nmodel providing
  upper performance bounds on supported microarchitectures,\ninsights into 
 workings of these microarchitectures gained during\ninvestigations are of 
 practical relevance to performance engineering.\n\nA quantitative power mo
 del for steady-state codes was developed that estimates\nprocessor power c
 onsumption based on core count, core and Uncore frequencies.\nMotivated by
  physical first principles the model resorts to fit parameters to\ndescrib
 e the relationship between core and Uncore frequencies to dissipated\npowe
 r; nevertheless, the mode's analytic nature enables insights into how\ndif
 ferent chip components interact with code and contribute to power\nconsump
 tion. To the best of my knowledge: It is the only analytic model that\ntak
 es all relevant processor parameters into account (active cores, various\n
 frequencies). Model quality is unprecedented (maximum relative model error
 \nover all examined applications, processors and parameters was 4%). Also,
  it is\nthe only analytic model that works for both scalable and saturatin
 g codes. The\nlatter is address with the help of the ECM model: By relatin
 g multi- to\nsingle-core performance estimates the application's parallel 
 efficiency is\ncalculated and per-core power consumption dampened accordin
 gly.\n\nBy combining the performance and power models an analytic energy m
 odel can be\nconstructed. The analytic nature of the energy model provides
  an point of\nentry for analytic deductions: Conclusions drawn from observ
 ations of\nempirical data can be derived analytically from the model, ther
 eby cementing\ntheir universality.\n\nIn addition to theoretical insights,
  the models can be used to identify\noptimum performance, energy-to-soluti
 on, and EDP and their corresponding\noperating points.  Determining the mo
 del parameters takes few measurements\n(six on processors with single cloc
 k domain, nine on those with separate clock\ndomains).  Assuming five-minu
 te samples (to reach temperature equilibrium), it\ntakes less than an hour
  to determine model parameters vs. two weeks to sweep\nall 3672 parameter 
 combinations of a Xeon E5-2697 processor (18 cores, 12 and\n17 different c
 ore and Uncore frequencies, respectively).\n\nPasses: Conference Pass, Exh
 ibition Pass, Computer Architecture, Energy consumption, HPC workflows, Pe
 rformance Analysis and Optimization\n\nTag: Conference Pass, Exhibition Pa
 ss, Computer Architecture, Energy consumption, HPC workflows, Performance 
 Analysis and Optimization
URL:https://2018.isc-program.com/presentation/?id=phd120&sess=sess103
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