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DTSTAMP:20191206T142456Z
LOCATION:Analog 1\, 2
DTSTART;TZID=Europe/Stockholm:20180627T100000
DTEND;TZID=Europe/Stockholm:20180627T110000
UID:isc_hpc_ISC High Performance 2018_sess148_apost109@linklings.com
SUMMARY:(A05) Poster from Japan: Accelerating HPC applications on FPGAs us
 ing OpenCL and FPGA Network
DESCRIPTION:HPC in Asia\n\n(A05) Poster from Japan: Accelerating HPC appli
 cations on FPGAs using OpenCL and FPGA Network\n\nFujita, Kobayashi, Yamag
 uchi, Abe, Yoshikawa...\n\nWe show two topics in this poster. One of them 
 is OpenCL-ready high-speed 40Gbit Ethernet FPGA networking. The other is o
 ptimizing space radiative transfer code using OpenCL. We add networking fu
 nctionality to the board support package (BSP) to use them from OpenCL. BS
 P is a hardware component to abstract differences between boards. Since th
 e BSP provided by the board vendor does not support all peripherals on the
  board, we have to add controllers for Ethernet to BSP. It achieves 1&#956
 ; sec latency and 4.97GB/s bandwidth (99.4% of the theoretical peak).\nAcc
 elerated Radiative transfer on grids Oct-Tree (ARGOT) is a program to solv
 e space radiative transfer problem and has been developed in Center for Co
 mputational Sciences (CCS), University of Tsukuba. Authentic Radiation Tra
 nsfer (ART) is one of algorithms used in ARGOT and is the dominant part of
  ARGOT program. We optimize ART algorithm to FPGAs using OpenCL. Our imple
 mentation uses channels to improve performance block RAMs in the FPGA chip
 . In performance comparison among FPGA, CPU and GPU, FPGA is 4.9 times fas
 ter than CPU and almost equal performance with GPU.\nAs future work, we wi
 ll combine the network and the application to realize Accelerator in Switc
 h (AiS) concept. It couples communications and computations tightly. We co
 nsider FPGAs can realize AiS because they can act as both of accelerators 
 and switches.\n\nPasses: Conference Pass
URL:https://2018.isc-program.com/presentation/?id=apost109&sess=sess148
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